Many types of electronic equipment, such as transceivers and other communications equipment, require differential comparators. Differential comparators are electrical circuits that compare two input signals, such as a differential signal, and generate an output that corresponds to the values of the input signals relative to each other. For example, a typical differential comparator will receive a reference signal and an input signal, such that the differential comparator will output a high (e.g., logic 1) signal when the voltage of the input signal is greater than the voltage of the reference signal and a low (e.g., logic 0) signal when the voltage of the input signal is less than the voltage of the reference signal.
The common mode voltage is the average voltage between a differential signal pair. Many communications architectures and standards require a certain range in which the common mode voltage of a differential signal resides. However, the common mode voltage range of a differential comparator is typically dictated by the performance limitations of its input stage. For example, the lower limit of the common mode voltage range in a differential comparator is limited by the voltage required to keep a differential pair in the input stage in a constant current region (saturation mode). In other words, the differential pair needs to operate in saturation mode for the differential comparator to function properly, and for the differential pair to operate in saturation mode, the common mode voltage needs to be sufficiently positive relative to the negative supply voltage of the differential comparator. Thus the common mode voltage range is significantly limited.
Techniques have been applied to circuit designs such that negative common mode voltage potentials can be accommodated in circuits that contain differential comparators. One example is a divide and shift network. A divide and shift network extends the common mode voltage range by compressing and DC shifting the differential input signal to create a common mode voltage that is within the operable range of a differential comparator. Thus, a differential signal is created that is proportional to the actual differential input signal, such that the common mode voltage signal of the proportional differential input signal can fall within the constraints of the differential comparator. This solution, however, consumes additional power, thus making it unsuitable for low power applications, such as communications devices operating in “sleep mode.”